WAFER LEVEL, CHIP SCALE SEMICONDUCTOR DEVICE PACKAGING COMPOSITIONS, AND METHODS RELATING THERETO

The invention relates generally to wafer level, chip scale semiconductor device packaging compositions capable of providing high density, small scale circuitry lines without the use of photolithography. The wafer level package comprises a stress buffer layer containing a polymer binder and a spinel...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Hauptverfasser:	LEE YUEH-LING, TSAI BIN-HONG, CHU JAMES, CHEN CHENGUNG
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

container_end_page
container_issue
container_start_page
container_title
container_volume
creator	LEE YUEH-LING TSAI BIN-HONG CHU JAMES CHEN CHENGUNG
description	The invention relates generally to wafer level, chip scale semiconductor device packaging compositions capable of providing high density, small scale circuitry lines without the use of photolithography. The wafer level package comprises a stress buffer layer containing a polymer binder and a spinel crystal filler in both a non-activated and a laser activated form. The stress buffer layer is patterned with a laser to thereby activate the filler, and the laser ablation path can then be selectively metalized.
format	Patent
fullrecord	<record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2010193950A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2010193950A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2010193950A13</originalsourceid><addsrcrecordid>eNqNyrEKwjAQANAuDqL-w4FrhVZx6Bgu1yaY5kpyrWMpEifRQv1_RPADnN7y1tl0VTUFcDSQywGN7SCicgSRWovsdY_CATQNFgk6hRfVWN8ActtxtGLZxxyU19CSGNYRAjkl3yKGAglvs9V9eixp93OT7WsSNIc0v8a0zNMtPdN77OOxKIuyOlXnQpWn_9YHYks0fA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>WAFER LEVEL, CHIP SCALE SEMICONDUCTOR DEVICE PACKAGING COMPOSITIONS, AND METHODS RELATING THERETO</title><source>esp@cenet</source><creator>LEE YUEH-LING ; TSAI BIN-HONG ; CHU JAMES ; CHEN CHENGUNG</creator><creatorcontrib>LEE YUEH-LING ; TSAI BIN-HONG ; CHU JAMES ; CHEN CHENGUNG</creatorcontrib><description>The invention relates generally to wafer level, chip scale semiconductor device packaging compositions capable of providing high density, small scale circuitry lines without the use of photolithography. The wafer level package comprises a stress buffer layer containing a polymer binder and a spinel crystal filler in both a non-activated and a laser activated form. The stress buffer layer is patterned with a laser to thereby activate the filler, and the laser ablation path can then be selectively metalized.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2010</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20100805&DB=EPODOC&CC=US&NR=2010193950A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25555,76308</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20100805&DB=EPODOC&CC=US&NR=2010193950A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>LEE YUEH-LING</creatorcontrib><creatorcontrib>TSAI BIN-HONG</creatorcontrib><creatorcontrib>CHU JAMES</creatorcontrib><creatorcontrib>CHEN CHENGUNG</creatorcontrib><title>WAFER LEVEL, CHIP SCALE SEMICONDUCTOR DEVICE PACKAGING COMPOSITIONS, AND METHODS RELATING THERETO</title><description>The invention relates generally to wafer level, chip scale semiconductor device packaging compositions capable of providing high density, small scale circuitry lines without the use of photolithography. The wafer level package comprises a stress buffer layer containing a polymer binder and a spinel crystal filler in both a non-activated and a laser activated form. The stress buffer layer is patterned with a laser to thereby activate the filler, and the laser ablation path can then be selectively metalized.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2010</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyrEKwjAQANAuDqL-w4FrhVZx6Bgu1yaY5kpyrWMpEifRQv1_RPADnN7y1tl0VTUFcDSQywGN7SCicgSRWovsdY_CATQNFgk6hRfVWN8ActtxtGLZxxyU19CSGNYRAjkl3yKGAglvs9V9eixp93OT7WsSNIc0v8a0zNMtPdN77OOxKIuyOlXnQpWn_9YHYks0fA</recordid><startdate>20100805</startdate><enddate>20100805</enddate><creator>LEE YUEH-LING</creator><creator>TSAI BIN-HONG</creator><creator>CHU JAMES</creator><creator>CHEN CHENGUNG</creator><scope>EVB</scope></search><sort><creationdate>20100805</creationdate><title>WAFER LEVEL, CHIP SCALE SEMICONDUCTOR DEVICE PACKAGING COMPOSITIONS, AND METHODS RELATING THERETO</title><author>LEE YUEH-LING ; TSAI BIN-HONG ; CHU JAMES ; CHEN CHENGUNG</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2010193950A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2010</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>LEE YUEH-LING</creatorcontrib><creatorcontrib>TSAI BIN-HONG</creatorcontrib><creatorcontrib>CHU JAMES</creatorcontrib><creatorcontrib>CHEN CHENGUNG</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>LEE YUEH-LING</au><au>TSAI BIN-HONG</au><au>CHU JAMES</au><au>CHEN CHENGUNG</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>WAFER LEVEL, CHIP SCALE SEMICONDUCTOR DEVICE PACKAGING COMPOSITIONS, AND METHODS RELATING THERETO</title><date>2010-08-05</date><risdate>2010</risdate><abstract>The invention relates generally to wafer level, chip scale semiconductor device packaging compositions capable of providing high density, small scale circuitry lines without the use of photolithography. The wafer level package comprises a stress buffer layer containing a polymer binder and a spinel crystal filler in both a non-activated and a laser activated form. The stress buffer layer is patterned with a laser to thereby activate the filler, and the laser ablation path can then be selectively metalized.</abstract><oa>free_for_read</oa></addata></record>
fulltext	fulltext_linktorsrc
identifier
ispartof
issn
language	eng
recordid	cdi_epo_espacenet_US2010193950A1
source	esp@cenet
subjects	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
title	WAFER LEVEL, CHIP SCALE SEMICONDUCTOR DEVICE PACKAGING COMPOSITIONS, AND METHODS RELATING THERETO
url	https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-15T00%3A51%3A29IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=LEE%20YUEH-LING&rft.date=2010-08-05&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2010193950A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true