WAFER LEVEL, CHIP SCALE SEMICONDUCTOR DEVICE PACKAGING COMPOSITIONS, AND METHODS RELATING THERETO

WAFER LEVEL, CHIP SCALE SEMICONDUCTOR DEVICE PACKAGING COMPOSITIONS, AND METHODS RELATING THERETO

The invention relates generally to wafer level, chip scale semiconductor device packaging compositions capable of providing high density, small scale circuitry lines without the use of photolithography. The wafer level package comprises a stress buffer layer containing a polymer binder and a spinel...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: LEE YUEH-LING, TSAI BIN-HONG, CHU JAMES, CHEN CHENGUNG
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:The invention relates generally to wafer level, chip scale semiconductor device packaging compositions capable of providing high density, small scale circuitry lines without the use of photolithography. The wafer level package comprises a stress buffer layer containing a polymer binder and a spinel crystal filler in both a non-activated and a laser activated form. The stress buffer layer is patterned with a laser to thereby activate the filler, and the laser ablation path can then be selectively metalized.