PROGRAMMABLE LOGIC BLOCK OF FPGA USING PHASE-CHANGE MEMORY DEVICE

PROGRAMMABLE LOGIC BLOCK OF FPGA USING PHASE-CHANGE MEMORY DEVICE

Provided is a programmable logic block of a field-programmable gate array (FPGA). The programmable logic block includes a pull-up access transistor connected to a power source, an up-phase-change memory device connected to the pull-up access transistor, a down-phase-change memory device connected to...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: KIM YONG-JOO, LEE SEUNG-YUN, PARK YOUNG SAM, JUNG SOONWON, YOON SUNG MIN, YU BYOUNG GON
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
PULSE TECHNIQUE
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Beschreibung
Zusammenfassung:Provided is a programmable logic block of a field-programmable gate array (FPGA). The programmable logic block includes a pull-up access transistor connected to a power source, an up-phase-change memory device connected to the pull-up access transistor, a down-phase-change memory device connected to the up-phase-change memory device, an output terminal between the up-phase-change memory device and the down-phase-change memory device, and a pull-down access transistor connected to the down-phase-change memory device and a ground. The resistance values of the up-phase-change memory device and the down-phase-change memory device are individually programmed.