TOLERANT BUFFER CIRCUIT AND INTERFACE

A tolerant buffer circuit and interface are provided in which reverse inflow of current to a power supply voltage from an output terminal does not occur even if the output terminal is at a higher potential than an output circuit power supply voltage during open-drain operation in an output circuit of a semiconductor integrated circuit, or if the output circuit power supply voltage becomes 0 V. Tolerant buffer circuit 100 is provided with PMOS transistors Q111 and Q112 that are connected in series and that share a source between power supply terminal VDD1 and output terminal 102, NMOS transistor Q113 connected between output terminal 102 and ground terminal 101, inverter 121 output-connected to the gate of PMOS transistor Q111, inverter 122 output-connected to the gate of PMOS transistor Q112, and control circuit 130 that outputs first, second, and third control signals to PMOS transistor Q111, PMOS transistor Q112, and NMOS transistor Q113 respectively, and controls the on/off state of these MOS transistors.