SEMICONDUCTOR DEVICE WITH INTERFACE CIRCUIT AND METHOD OF CONFIGURING SEMICONDUCTOR DEVICES

Methods and devices yielding an improved semiconductor device with interface circuit are disclosed. Configuring a semiconductor with parallel device features reduces process variation (e.g., lithographically-induced process variation or other defects). Embodiments of the present invention provide se...

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1. Verfasser:	HOSOMI EIICHI
Format:	Patent
Sprache:	eng
Schlagworte:	AUXILIARY PROCESSES IN PHOTOGRAPHY BASIC ELECTRIC ELEMENTS CINEMATOGRAPHY CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION ORPROCESSING OF GOODS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY ELECTROGRAPHY GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS HOLOGRAPHY PHOTOGRAPHIC PROCESSES, e.g. CINE, X-RAY, COLOUR,STEREO-PHOTOGRAPHIC PROCESSES PHOTOGRAPHY PHOTOSENSITIVE MATERIALS FOR PHOTOGRAPHIC PURPOSES PHYSICS SEMICONDUCTOR DEVICES TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINSTCLIMATE CHANGE
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Beschreibung
Zusammenfassung:	Methods and devices yielding an improved semiconductor device with interface circuit are disclosed. Configuring a semiconductor with parallel device features reduces process variation (e.g., lithographically-induced process variation or other defects). Embodiments of the present invention provide semiconductor devices with I/O cell device features (e.g., I/O gates or core gates) laid out in parallel. Additionally, embodiments of the present invention can allow patterning devices to be made to more exacting tolerances because some patterning devices may have a higher capability along one axis than another. Embodiments of the present invention also include a semiconductor device having like-functioned I/O cells arranged such that their layouts and rotational orientations with respect to their corresponding core remain constant. Furthermore, disclosed semiconductor devices may include at least one circuit cell having non-parallel features, where the circuit cell is arranged either within the core or within a corresponding interface circuit cell.