PHASE/FREQUENCY DETECTOR FOR A PHASE-LOCKED LOOP THAT SAMPLES ON BOTH RISING AND FALLING EDGES OF A REFERENCE SIGNAL

A circuit comprises a first phase detector, a second phase detector, and combinational logic. The first phase detector is for detecting a phase difference between a rising edge of a first clock signal and a rising edge of a second clock signal, and for providing a first difference signal indicating the phase difference. The second phase detector is for detecting a phase difference at a time of a falling edge of the first clock signal and a time of a falling edge of the second clock signal, and for providing a second difference signal indicating the phase difference. The combinational logic is coupled to receive the first difference signal and the second difference signal, and for preventing the second difference signal from being provided when the first difference signal is being provided.