TEST CIRCUIT AND TEST METHOD

A test circuit with which the cost for checking the duty ratio of a clock signal is restrained. A sampling timing generating circuit, to which the measurement-target clock signal MCK is input, outputs first and second sampling trigger signals to A sample-and-hold circuit 102 respective prescribed ti...

Ausführliche Beschreibung

Bibliographische Detailangaben

1. Verfasser:	SUMI YOSHIKAZU
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS BASIC ELECTRONIC CIRCUITRY ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS PULSE TECHNIQUE SEMICONDUCTOR DEVICES TESTING
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