TEST CIRCUIT AND TEST METHOD

A test circuit with which the cost for checking the duty ratio of a clock signal is restrained. A sampling timing generating circuit, to which the measurement-target clock signal MCK is input, outputs first and second sampling trigger signals to A sample-and-hold circuit 102 respective prescribed ti...

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Bibliographische Detailangaben
1. Verfasser:	SUMI YOSHIKAZU
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS BASIC ELECTRONIC CIRCUITRY ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS PULSE TECHNIQUE SEMICONDUCTOR DEVICES TESTING
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Beschreibung
Zusammenfassung:	A test circuit with which the cost for checking the duty ratio of a clock signal is restrained. A sampling timing generating circuit, to which the measurement-target clock signal MCK is input, outputs first and second sampling trigger signals to A sample-and-hold circuit 102 respective prescribed timings before and after a timing that is one-half period of the measurement-target clock signal after a first edge of the measurement-target clock signal. The sample-and-hold circuit samples and holds the measurement-target clock signal in correspondence with respective ones of the first and second sampling trigger signals. The sample-and-hold circuit forms all or part of a scan path and outputs a signal, which is being held for checking the duty ratio, from a scan output terminal in response to a scan clock signal.