VARIOUS METHODS AND APPARATUS FOR ADDRESS TILING AND CHANNEL INTERLEAVING THROUGHOUT THE INTEGRATED SYSTEM

Various methods and apparatus are described for a target with multiple channels. Address decoding logic is configured to implement a distribution of requests from individual burst requests to two or more memory channels making up an aggregate target. The address decoding logic implements a channel-s...

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Hauptverfasser:	CHOU CHIENUN, SRINIVASAN KRISHNAN, WINGARD DREW E
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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