VARIOUS METHODS AND APPARATUS FOR ADDRESS TILING AND CHANNEL INTERLEAVING THROUGHOUT THE INTEGRATED SYSTEM

VARIOUS METHODS AND APPARATUS FOR ADDRESS TILING AND CHANNEL INTERLEAVING THROUGHOUT THE INTEGRATED SYSTEM

Various methods and apparatus are described for a target with multiple channels. Address decoding logic is configured to implement a distribution of requests from individual burst requests to two or more memory channels making up an aggregate target. The address decoding logic implements a channel-s...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: CHOU CHIENUN, SRINIVASAN KRISHNAN, WINGARD DREW E
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:Various methods and apparatus are described for a target with multiple channels. Address decoding logic is configured to implement a distribution of requests from individual burst requests to two or more memory channels making up an aggregate target. The address decoding logic implements a channel-selection hash function to allow requests from each individual burst request to be distributed amongst the two or more channels in a non-linear sequential pattern in channel round order that make up the aggregate target.