SHADER INTERFACES

Allocation of memory registers for shaders by a processor is described herein. For each shader, registers are allocated based on the shader's level of complexity. Simpler shader instances are restricted to a smaller number of memory registers. More complex shader instances are allotted more reg...

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Bibliographische Detailangaben
Hauptverfasser:	RAPP JOHN L, LACEY MARK M, PEEPER CRAIG, ONEPPO MICHAEL V, BLISS ANDREW L
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING IMAGE DATA PROCESSING OR GENERATION, IN GENERAL PHYSICS
Online-Zugang:	Volltext bestellen
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Beschreibung
Zusammenfassung:	Allocation of memory registers for shaders by a processor is described herein. For each shader, registers are allocated based on the shader's level of complexity. Simpler shader instances are restricted to a smaller number of memory registers. More complex shader instances are allotted more registers. To do so, developers' high level shading level (HLSL) language includes template classes of shaders that can later be replaced by complex or simple versions of the shader. The HLSL is converted to bytecode that can be used to rasterize pixels on a computing device.