Semiconductor integrated circuit design method and semiconductor integrated circuit design apparatus

A semiconductor integrated circuit design method includes referring to a best worst coefficient file which stores variation coefficients of capacitance and resistance in each of plural wiring layers under a best condition and a worst condition to form a wiring which is a critical path in a first layer with the smallest variation out of the plural wiring layers, extracting capacitance and resistance corresponding to a wiring layout of the plural wiring layers as a capacitance resistance file, referring to the capacitance resistance file and the best worst coefficient file to generate a best worst capacitance resistance file where capacitance and resistance are defined with taking into consideration the variation on the wiring in each of the plural wiring layers, and performing timing verification of the wiring which is the critical path on the basis of the best worst capacitance resistance file.