METHOD FOR SELECTIVELY REMOVING A SPACER IN A DUAL STRESS LINER APPROACH

METHOD FOR SELECTIVELY REMOVING A SPACER IN A DUAL STRESS LINER APPROACH

By integrating a spacer removal process into the sequence for patterning a first stress-inducing material during a dual stress liner approach, the sidewall spacer structure for one type of transistor may be maintained, without requiring additional lithography steps.

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Bibliographische Detailangaben
Hauptverfasser: FROHBERG KAI, SALZ HEIKE, BERTHOLD HEIKE, GRIMM VOLKER
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:By integrating a spacer removal process into the sequence for patterning a first stress-inducing material during a dual stress liner approach, the sidewall spacer structure for one type of transistor may be maintained, without requiring additional lithography steps.