POWER SAVINGS WITH A LEVEL-SHIFTING BOUNDARY ISOLATION FLIP-FLOP (LSIFF) AND A CLOCK CONTROLLED DATA RETENTION SCHEME

POWER SAVINGS WITH A LEVEL-SHIFTING BOUNDARY ISOLATION FLIP-FLOP (LSIFF) AND A CLOCK CONTROLLED DATA RETENTION SCHEME

An apparatus for providing active mode power reduction for circuits having data retention includes a master slave flip flop (MSFF) for latching a data input. An output level shifter (OLS), coupled to the MSFF, retains the data input in response to the MSFF being operable in an active power saving mo...

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Bibliographische Detailangaben
Hauptverfasser: WANG ALICE, KO UMING U, MAIR HUGH T, VILANGUDIPITCHAI RAMAPRASATH, GURURAJARAO SUMANTH KATTE, HONNAVARA-PRASAD SUSHMA
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
INFORMATION STORAGE
PHYSICS
PULSE TECHNIQUE
STATIC STORES
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Beschreibung
Zusammenfassung:An apparatus for providing active mode power reduction for circuits having data retention includes a master slave flip flop (MSFF) for latching a data input. An output level shifter (OLS), coupled to the MSFF, retains the data input in response to the MSFF being operable in an active power saving mode (APSM) to reduce power. The OLS operating in the APSM provides a level shifter output having a configurable voltage, thereby providing output isolation. A change in an operating mode of the MSFF between an active mode and the APSM is independent of a retention (RET) mode input.