CIRCUIT AND METHOD FOR A GATE CONTROL CIRCUIT WITH REDUCED VOLTAGE STRESS

Circuit and method for a gate control output circuit having reduced voltage stress on the devices is disclosed. In a circuit of MOS transistors for supplying an output to control a transfer gate, the output having a high voltage level that exceeds a supply voltage, first and second clamping circuits...

Ausführliche Beschreibung

Bibliographische Detailangaben

1. Verfasser:	JUNG TAE HYUNG
Format:	Patent
Sprache:	eng
Schlagworte:	CONTROLLING PHYSICS REGULATING SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
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