System for simplifying layout processing

A system and method for integrated circuit design are disclosed to enhance manufacturability of circuit layouts by applying layout processing to handle imperfections such as jogs in integrated circuit design layouts. The layout processing may be applied to jogs in the original integrated circuit des...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: ZHANG YOUPING, LAI WEINONG
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:A system and method for integrated circuit design are disclosed to enhance manufacturability of circuit layouts by applying layout processing to handle imperfections such as jogs in integrated circuit design layouts. The layout processing may be applied to jogs in the original integrated circuit design layout or jogs created post-design by process biases, as well as design rule check and Boolean processes or process compensation.