Method of modeling and employing the CMOS gate slew and output load dependent pin capacitance during timing analysis

An accurate method to compute the capacitance at a pin whose capacitance is slew dependant. The method uses existing library characterized data and provides an equation based approach which can easily be integrated in static timing analysis without the added resource needs that an iterative approach would require. An RC/RLC network from slew and output load dependent pin capacitance tables is generated. The resulting linear network which models the pin capacitance is then stitched to the original interconnect network and used to calculate the propagation delay across a gate and corresponding interconnect. The method steps include: a) determining a response of the gate pin capacitance to its input slew and output load; b) synthesizing a linear time-invariant filter that matches the response; c) extending the interconnect model to include the synthesized time-invariant filter; and d) inputting the extended interconnect model into a static timing analysis for determining timing behavior between a gate input and each of its fan-out gates.