TEST QUALITY EVALUATING AND IMPROVING SYSTEM FOR SEMICONDUCTOR INTEGRATED CIRCUIT AND TEST QUALITY EVALUATION AND IMPROVEMENT METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT

A test quality evaluating and improving system has a fault-layout information link section which creates a weighted fault dictionary by correlating a layout element related to an undetected fault, out of faults corresponding to a specified fault model and occurring in a circuit to be tested, with th...

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Bibliographische Detailangaben

1. Verfasser:	NOZUYAMA YASUYUKI
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS TESTING
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