TEST QUALITY EVALUATING AND IMPROVING SYSTEM FOR SEMICONDUCTOR INTEGRATED CIRCUIT AND TEST QUALITY EVALUATION AND IMPROVEMENT METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT

A test quality evaluating and improving system has a fault-layout information link section which creates a weighted fault dictionary by correlating a layout element related to an undetected fault, out of faults corresponding to a specified fault model and occurring in a circuit to be tested, with the undetected fault as a weight of the undetected fault which cannot be detected by a test pattern for testing the faults; a test quality measure calculating section which multiplies the weight of the undetected fault, the failure mode-fault model correlation factor for correlating the failure mode of the layout element and the fault model, and the failure occurrence rate of each layout element, and outputs an obtained product as a failure remaining rate of the test pattern; a determining section; and a test point inserting section.