ERROR CORRECTION IN AN INTEGRATED CIRCUIT WITH AN ARRAY OF MEMORY CELLS

ERROR CORRECTION IN AN INTEGRATED CIRCUIT WITH AN ARRAY OF MEMORY CELLS

An integrated circuit includes an array of memory cells, and an error correction code circuit configured to correct errors in data read from the array based at least in part on a map that identifies locations of erratic memory cells in the array.

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Bibliographische Detailangaben
Hauptverfasser: KREUPL FRANZ, DEAMBROGGI LUCA, STEINLESBERGER GERNOT, DUC CHRISTIAN PHO, PHILIPP JAN BORIS, HAPP THOMAS, SCHROGMEIER PETER
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:An integrated circuit includes an array of memory cells, and an error correction code circuit configured to correct errors in data read from the array based at least in part on a map that identifies locations of erratic memory cells in the array.