IC Design Flow Incorporating Optimal Assumptions of Power Supply Voltage Drops at Cells when Performing Timing Analysis

An aspect of the present invention selects a maximum voltage and a minimum voltage in respective sub-intervals of a timing window in which the output of a cell is expected to switch, and performing timing analysis based on the selected values. By using appropriate smaller sub-intervals within the timing window, more optimal physical layout of the design may be obtained. In an embodiment, the sub-intervals equal a cell delay, i.e., the delay between an input change to an output change for the corresponding cell. According to another aspect of the present invention, the sub-interval for later cells in a timing path are modified based on modified timing window of previous cells in the path, to reduce the computational requirement.