METHOD AND SYSTEM FOR ANALYZING A COMPLETION DELAY IN A PROCESSOR USING AN ADDITIVE STALL COUNTER

In a data processing system having a set of components for performing a set of operations, in which one or more of the set of operations has processing dependencies with respect to other of the set of operations, a method for using an additive stall counter to analyze a completion delay is disclosed. The method includes initiating execution of a group of instructions and a performance monitor unit resetting a value stored within the additive stall counter. The method further includes the performance monitor unit incrementing the value within the additive stall counter until all instructions within the group of instructions complete. In response to all instructions within the group of instructions completing a cause of the completion delay is determined. In response to determining that the delay was caused by the first stall cause, the value stored within the additive stall counter is added to a first performance monitor counter designated for the first stall cause, and, in response to determining that the delay was caused by a second stall cause, the value stored within the additive stall counter is added to a second performance monitor counter designated for the second stall cause.