CHIP SCALE STACKED DIE PACKAGE

A die prepared for stacking in a chip scale stacked die assembly, having interconnect sites in an area inward from a die edge and interconnect pads near at least one die edge. Second-level interconnection of the stacked die assembly can be made by way of connections between a first die in the assemb...

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Bibliographische Detailangaben
Hauptverfasser: MCELREA SIMON J.S, DU YONG, ROBINSON MARC E, CASKEY TERRENCE, ANDREWS, JR. LAWRENCE DOUGLAS, VINDASIUS AL, MCGRATH SCOTT
Format: Patent
Sprache:eng
Schlagworte:
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Beschreibung
Zusammenfassung:A die prepared for stacking in a chip scale stacked die assembly, having interconnect sites in an area inward from a die edge and interconnect pads near at least one die edge. Second-level interconnection of the stacked die assembly can be made by way of connections between a first die in the assembly and circuitry on a support; and interconnection between die in the stack can be made by way of connection of z-interconnects with bonds pads in the die attach side of the support near or at one or more die edges. Methods for preparing the die include processes carried out to an advanced stage at the wafer level or at the die array level.