Soft-reconfigurable massively parallel architecture and programming system

The present disclosure provides an architecture that enables massive parallel processing on an IC while alleviating control congestion, memory access congestion and wiring congestion, together with high flexibility where the processing units are soft-arranged to perform different tasks. In an embodi...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	MITRA HIRAK, KULKARNI RAJ, WICKS RICHARD, MOON MICHAEL
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRONIC CIRCUITRY ELECTRICITY PULSE TECHNIQUE
Online-Zugang:	Volltext bestellen
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