Soft-reconfigurable massively parallel architecture and programming system

The present disclosure provides an architecture that enables massive parallel processing on an IC while alleviating control congestion, memory access congestion and wiring congestion, together with high flexibility where the processing units are soft-arranged to perform different tasks. In an embodi...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: MITRA HIRAK, KULKARNI RAJ, WICKS RICHARD, MOON MICHAEL
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:The present disclosure provides an architecture that enables massive parallel processing on an IC while alleviating control congestion, memory access congestion and wiring congestion, together with high flexibility where the processing units are soft-arranged to perform different tasks. In an embodiment, the present architecture includes a functional block with a GO component to start the functional block, and a DONE component to identifying the completion status. The GO and DONE components can be linked together, preferably by a linkage component, to chain the functional blocks. The linkage is preferably soft configurable. In another embodiment, the present architecture includes an integrated circuit comprises a plurality of functional blocks chained together for serial processing, parallel processing, or any combination thereof.