PACKAGED INTEGRATED CIRCUIT AND METHOD OF FORMING THEREOF

Disclosed is a packaged integrated circuit and a method of forming thereof. The packaged integrated circuit includes a substrate, a plurality of solder bumps, a semiconductor die and a plurality of copper bumps. The plurality of solder bumps are configured on the substrate. Each of the plurality of solder bumps has a height of about 40 micrometers (mum) to about 65 mum. Further, the plurality of copper bumps are configured on the semiconductor die. Each of the plurality of copper bumps has a height of about 10 mum to about 25 mum. The semiconductor die is disposed above the substrate such that the plurality of copper bumps are coupled to the plurality of solder bumps, which in turn, couples the semiconductor die to the substrate.