POLYGONAL AREA DESIGN RULE CORRECTION METHOD FOR VLSI LAYOUTS

A method of polygonal area design rule correction for use in an electronic design automation tool for governing integrated circuit (IC) design layouts using one-dimensional (1-D) optimization, with steps of analyzing IC design layout data to identify violating polygons, partitioning violating polygo...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	GRAY MICHAEL S, YUAN XIN, HIBBELER JASON D, GUZOWSKI MATTHEW T, WALKER ROBERT F
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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