POLYGONAL AREA DESIGN RULE CORRECTION METHOD FOR VLSI LAYOUTS

A method of polygonal area design rule correction for use in an electronic design automation tool for governing integrated circuit (IC) design layouts using one-dimensional (1-D) optimization, with steps of analyzing IC design layout data to identify violating polygons, partitioning violating polygons into rectangles in a direction of optimization, formulating an area constraint for each violating polygon to formulate a global linear programming (LP) problem that includes each constraint for each violating polygon and solving the global LP problem to obtain a real-valued solution. A next LP problem is created for each area constraint, and solved. The creating a next and solving the next LP problem and solving are repeated until the last "next LP problem" is solved using constraints and objectives representing sums or differences of no more than two optimization variables.