CIRCUIT ARRANGEMENT AND METHOD FOR LIMITING A SIGNAL VOLTAGE

The present invention relates to the field of signal processing. It is an object of the invention to provide a circuit arrangement (VL) and a method for limiting a signal voltage upstream of a processing stage (A) of a signal processing device, by means of which circuit arrangement and method it becomes possible to reduce signal interference. It is provided a voltage comparison (OPAMP 2 ) within a closed-loop control of an output signal (Vin'), by means of which closed-loop control the value of said output signal (Vin') is limited to a maximum value (Vmax/2). Thus, it becomes possible to prevent the generation of signal interference during signal processing. The voltage limiting method according to the invention uses as a reference quantity a reference voltage (Vmax/2) to which the output signal (Vin') is compared in the context of closed-loop control. A closed-loop control deviation signal of this closed-loop control controls the variable-resistance voltage divider component (T 1 ) at which the output signal (Vin') is formed, e.g. directly picked up, as a voltage drop.