MOS TRANSISTORS HAVING HIGH-K OFFSET SPACERS THAT REDUCE EXTERNAL RESISTANCE AND METHODS FOR FABRICATING THE SAME

MOS transistors having high-k spacers and methods for fabricating such transistors are provided. One exemplary method comprises forming a gate stack overlying a semiconductor substrate and forming an offset spacer about sidewalls of the gate stack. The offset spacer is formed of a high-k dielectric...

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Bibliographische Detailangaben
Hauptverfasser: HARGROVE MICHAEL, YANG FRANK (BIN)
Format: Patent
Sprache:eng
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Zusammenfassung:MOS transistors having high-k spacers and methods for fabricating such transistors are provided. One exemplary method comprises forming a gate stack overlying a semiconductor substrate and forming an offset spacer about sidewalls of the gate stack. The offset spacer is formed of a high-k dielectric material that results in a low interface trap density between the offset spacer and the semiconductor substrate. First ions of a conductivity-determining impurity type are implanted into the semiconductor substrate using the gate stack and the offset spacer as an implantation mask to form spaced-apart impurity-doped extensions.