INSTRUCTION-BASED TIMER CONTROL DURING DEBUG

INSTRUCTION-BASED TIMER CONTROL DURING DEBUG

A processing device includes a timer and a processor core configured to execute an instruction during a debug session. The processing device further includes a timer control module configured to selectively enable/disable the timer based on a characteristic of the instruction. Another processing dev...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: MOYER WILLIAM C, NEARING JASON T
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:A processing device includes a timer and a processor core configured to execute an instruction during a debug session. The processing device further includes a timer control module configured to selectively enable/disable the timer based on a characteristic of the instruction. Another processing device includes a timer, a processor core configured to single step execute a sequence of instructions during a debug session, and a timer control module configured to selectively enable/disable the timer during single step execution of each instruction of the sequence of instructions.