Methods and apparatus for improving error indication performance in systems with low-density parity check codes

The present invention is directed to methods and apparatus for improving error indication performance in systems employing low-density parity check (LDPC) codes. In one aspect, a method and apparatus for providing error indication based on full LDPC parity check re-encoding are provided. In an embod...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: KRAVITZ DAVID, LIU JIANHAN, MACMULLAN SAMUEL J, THANGARAJ ANDREW
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator KRAVITZ DAVID
LIU JIANHAN
MACMULLAN SAMUEL J
THANGARAJ ANDREW
description The present invention is directed to methods and apparatus for improving error indication performance in systems employing low-density parity check (LDPC) codes. In one aspect, a method and apparatus for providing error indication based on full LDPC parity check re-encoding are provided. In an embodiment, an LDPC encoder is employed at the receiver to re-encode the parity bits. In another embodiment, the parity bits are re-encoded recursively based on information readily available at the decoder of the receiver. In another aspect, a method and apparatus for providing error indication based on partial LDPC parity check re-encoding are provided. In an embodiment, partial checksum information is determined based on the decoder output and used to provide error indication. In a further aspect, a hybrid CRC checking and LDPC parity check re-encoding approach is provided. This approach further enhances error indication performance by reducing the miss probability compared to pure LDPC parity check re-encoding.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2008155372A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2008155372A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2008155372A13</originalsourceid><addsrcrecordid>eNqNjLsKwkAQRdNYiPoPA9aBPAjaiig2Vmodht2JWUx2lp3RkL83AT_A6nAuh7tM-ErashVAbwFDwIj6Fmg4gutD5I_zT6AYZ_fWGVTHHgLFqejRG5pmkFGUeoHBaQsdD6klL05HmO5mmJbMCwxbknWyaLAT2vy4Srbn0_14SSlwTRLQkCetH7ciy_Z5VZW74pCX_1VfjaNEsw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Methods and apparatus for improving error indication performance in systems with low-density parity check codes</title><source>esp@cenet</source><creator>KRAVITZ DAVID ; LIU JIANHAN ; MACMULLAN SAMUEL J ; THANGARAJ ANDREW</creator><creatorcontrib>KRAVITZ DAVID ; LIU JIANHAN ; MACMULLAN SAMUEL J ; THANGARAJ ANDREW</creatorcontrib><description>The present invention is directed to methods and apparatus for improving error indication performance in systems employing low-density parity check (LDPC) codes. In one aspect, a method and apparatus for providing error indication based on full LDPC parity check re-encoding are provided. In an embodiment, an LDPC encoder is employed at the receiver to re-encode the parity bits. In another embodiment, the parity bits are re-encoded recursively based on information readily available at the decoder of the receiver. In another aspect, a method and apparatus for providing error indication based on partial LDPC parity check re-encoding are provided. In an embodiment, partial checksum information is determined based on the decoder output and used to provide error indication. In a further aspect, a hybrid CRC checking and LDPC parity check re-encoding approach is provided. This approach further enhances error indication performance by reducing the miss probability compared to pure LDPC parity check re-encoding.</description><language>eng</language><subject>BASIC ELECTRONIC CIRCUITRY ; CALCULATING ; CODE CONVERSION IN GENERAL ; CODING ; COMPUTING ; COUNTING ; DECODING ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRICITY ; PHYSICS</subject><creationdate>2008</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20080626&amp;DB=EPODOC&amp;CC=US&amp;NR=2008155372A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20080626&amp;DB=EPODOC&amp;CC=US&amp;NR=2008155372A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KRAVITZ DAVID</creatorcontrib><creatorcontrib>LIU JIANHAN</creatorcontrib><creatorcontrib>MACMULLAN SAMUEL J</creatorcontrib><creatorcontrib>THANGARAJ ANDREW</creatorcontrib><title>Methods and apparatus for improving error indication performance in systems with low-density parity check codes</title><description>The present invention is directed to methods and apparatus for improving error indication performance in systems employing low-density parity check (LDPC) codes. In one aspect, a method and apparatus for providing error indication based on full LDPC parity check re-encoding are provided. In an embodiment, an LDPC encoder is employed at the receiver to re-encode the parity bits. In another embodiment, the parity bits are re-encoded recursively based on information readily available at the decoder of the receiver. In another aspect, a method and apparatus for providing error indication based on partial LDPC parity check re-encoding are provided. In an embodiment, partial checksum information is determined based on the decoder output and used to provide error indication. In a further aspect, a hybrid CRC checking and LDPC parity check re-encoding approach is provided. This approach further enhances error indication performance by reducing the miss probability compared to pure LDPC parity check re-encoding.</description><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>CALCULATING</subject><subject>CODE CONVERSION IN GENERAL</subject><subject>CODING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>DECODING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRICITY</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2008</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjLsKwkAQRdNYiPoPA9aBPAjaiig2Vmodht2JWUx2lp3RkL83AT_A6nAuh7tM-ErashVAbwFDwIj6Fmg4gutD5I_zT6AYZ_fWGVTHHgLFqejRG5pmkFGUeoHBaQsdD6klL05HmO5mmJbMCwxbknWyaLAT2vy4Srbn0_14SSlwTRLQkCetH7ciy_Z5VZW74pCX_1VfjaNEsw</recordid><startdate>20080626</startdate><enddate>20080626</enddate><creator>KRAVITZ DAVID</creator><creator>LIU JIANHAN</creator><creator>MACMULLAN SAMUEL J</creator><creator>THANGARAJ ANDREW</creator><scope>EVB</scope></search><sort><creationdate>20080626</creationdate><title>Methods and apparatus for improving error indication performance in systems with low-density parity check codes</title><author>KRAVITZ DAVID ; LIU JIANHAN ; MACMULLAN SAMUEL J ; THANGARAJ ANDREW</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2008155372A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2008</creationdate><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>CALCULATING</topic><topic>CODE CONVERSION IN GENERAL</topic><topic>CODING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>DECODING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRICITY</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>KRAVITZ DAVID</creatorcontrib><creatorcontrib>LIU JIANHAN</creatorcontrib><creatorcontrib>MACMULLAN SAMUEL J</creatorcontrib><creatorcontrib>THANGARAJ ANDREW</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KRAVITZ DAVID</au><au>LIU JIANHAN</au><au>MACMULLAN SAMUEL J</au><au>THANGARAJ ANDREW</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Methods and apparatus for improving error indication performance in systems with low-density parity check codes</title><date>2008-06-26</date><risdate>2008</risdate><abstract>The present invention is directed to methods and apparatus for improving error indication performance in systems employing low-density parity check (LDPC) codes. In one aspect, a method and apparatus for providing error indication based on full LDPC parity check re-encoding are provided. In an embodiment, an LDPC encoder is employed at the receiver to re-encode the parity bits. In another embodiment, the parity bits are re-encoded recursively based on information readily available at the decoder of the receiver. In another aspect, a method and apparatus for providing error indication based on partial LDPC parity check re-encoding are provided. In an embodiment, partial checksum information is determined based on the decoder output and used to provide error indication. In a further aspect, a hybrid CRC checking and LDPC parity check re-encoding approach is provided. This approach further enhances error indication performance by reducing the miss probability compared to pure LDPC parity check re-encoding.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US2008155372A1
source esp@cenet
subjects BASIC ELECTRONIC CIRCUITRY
CALCULATING
CODE CONVERSION IN GENERAL
CODING
COMPUTING
COUNTING
DECODING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
title Methods and apparatus for improving error indication performance in systems with low-density parity check codes
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-09T16%3A49%3A30IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=KRAVITZ%20DAVID&rft.date=2008-06-26&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2008155372A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true