Methods and apparatus for improving error indication performance in systems with low-density parity check codes

The present invention is directed to methods and apparatus for improving error indication performance in systems employing low-density parity check (LDPC) codes. In one aspect, a method and apparatus for providing error indication based on full LDPC parity check re-encoding are provided. In an embod...

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Bibliographische Detailangaben
Hauptverfasser: KRAVITZ DAVID, LIU JIANHAN, MACMULLAN SAMUEL J, THANGARAJ ANDREW
Format: Patent
Sprache:eng
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Zusammenfassung:The present invention is directed to methods and apparatus for improving error indication performance in systems employing low-density parity check (LDPC) codes. In one aspect, a method and apparatus for providing error indication based on full LDPC parity check re-encoding are provided. In an embodiment, an LDPC encoder is employed at the receiver to re-encode the parity bits. In another embodiment, the parity bits are re-encoded recursively based on information readily available at the decoder of the receiver. In another aspect, a method and apparatus for providing error indication based on partial LDPC parity check re-encoding are provided. In an embodiment, partial checksum information is determined based on the decoder output and used to provide error indication. In a further aspect, a hybrid CRC checking and LDPC parity check re-encoding approach is provided. This approach further enhances error indication performance by reducing the miss probability compared to pure LDPC parity check re-encoding.