HORIZONTAL SYNCHRONOUS CIRCUIT, DISPLAY DEVICE, AND CLOCK ADJUSTING METHOD

This horizontal synchronous circuit is a horizontal synchronous circuit generating a first horizontal synchronizing signal synchronous with a second horizontal synchronizing signal included in a video signal, and includes: a PLL oscillator generating a pixel clock signal; a phase comparator outputting a difference signal of the first horizontal synchronizing signal and the second horizontal synchronizing signal; a filter filtering the difference signal with a predetermined time constant to output, to the PLL oscillator, the resultant as a correction signal for the PLL oscillator; a counter divider counting the pixel clock signal generated by the PLL oscillator and outputting a pulse signal every predetermined count number to generate the first horizontal synchronizing signal; and a count controller temporarily changing the time constant of the filter based on an instruction from a user and controlling the count number of the counter divider while the time constant is changed.