Clock duty changing apparatus

A clock duty changing apparatus changes a duty ratio of an input clock signal with nearly 50% duty ratio to a target value being externally supplied and outputs the input clock signal thereinafter as an output signal. The apparatus includes a duty regulation circuit and a duty correction circuit. The duty regulation circuit includes a delay selection circuit and an operation circuit. The delay selection circuit generates a delay signal by delaying the input clock signal by delay time determined based on a first control signal and a second control signal. The first control signal is externally supplied to the apparatus. The second control signal is generated by the duty correction circuit so that mismatch between the duty ratio of the output clock signal and the target value is reduced. The operation circuit generates the output clock signal by logic operation using the delay signal and the input clock signal.