HIGH PERFORMANCE SINGLE EVENT UPSET HARDENED SRAM CELL

HIGH PERFORMANCE SINGLE EVENT UPSET HARDENED SRAM CELL

An SRAM cell. The SRAM cell includes a first CMOS inverter and a second CMOS inverter, an input of the first inverter connected to an output of the second inverter and an input of the second inverter connected to an output of the first inverter, a first MOSFET interposed between an output of the fir...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: HORAK DAVID VACLAV, FURUKAWA TOSHIHARU, CANNON ETHAN HARRISON, KOBURGER CHARLES WILLIAM, MANDELMAN JACK A
Format: Patent
Sprache:eng
Schlagworte:
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Beschreibung
Zusammenfassung:An SRAM cell. The SRAM cell includes a first CMOS inverter and a second CMOS inverter, an input of the first inverter connected to an output of the second inverter and an input of the second inverter connected to an output of the first inverter, a first MOSFET interposed between an output of the first CMOS inverter and a first plate of a first capacitor, a second plate of the first capacitor connected to a high voltage terminal of a power supply; a second MOSFET interposed between an output of the second CMOS inverter and a first plate of a second capacitor, a second plate of the second capacitor connected to the high voltage terminal of the power supply; and a control signal line connected to a gate of the first MOSFET and a gate of the second MOSFET.