MULTIPLEXER CIRCUIT WITH COMBINED LEVEL SHIFTING AND DELAY CONTROL FUNCTIONS

A digitally controlled circuit is arranged to provide the combined functions of level shifting, multiplexing, and delay control functions. The circuit is compact, and uses lower power and lower overall noise susceptibility over other solutions. A programmable bias current is arranged to adjust the delay through the circuit. The bias current can be provided by a digitally controlled current source, a binary weighted current DAC, or other digitally controlled means. The multiplexing functions are provided by an input stage circuit that is current limited by the programmable bias current. An output stage is arranged to convert signals from the input stage to a desired voltage level.