DIGITAL ADJUSTMENT OF AN OSCILLATOR

The invention concerns the adjustment of an oscillation frequency of an oscillator, in particular the digital coarse adjustment of a PLL oscillator by means of a circuit arrangement comprising at least one pair of capacitors (C, C'), of which first terminals are connected with the oscillator, and second terminals can selectively be connected by means of a switching arrangement with a first reference potential (vss), in order to incorporate the capacitor pair (C, C') into an oscillating circuit of the oscillator, wherein the circuit arrangement comprises: first FETs (T 1, T 1 ') for the respective connection of the second terminals with the first reference potential (vss), a second FET (T 2 ) for the connection of the second terminals with each other, and third FETs (T 3, T 3 ') for the respective connection of the second terminals with a second reference potential (vdd), which differs from the first reference potential (vss).