Method and System for Logic Equivalence Checking

Method and System for Logic Equivalence Checking

Some embodiments relate to a method and apparatus for performing logic equivalence checking (EC) of circuits using adaptive learning based on a persistent cache containing information on sub-problems solved from previous equivalency checking runs. These sub-problems can include basic EC tasks such a...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: LIN CHIHANG, LAI YUNG-TE, KHOO KEI-YONG, PANDEY MANISH, SIARKOWSKI BRET
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:Some embodiments relate to a method and apparatus for performing logic equivalence checking (EC) of circuits using adaptive learning based on a persistent cache containing information on sub-problems solved from previous equivalency checking runs. These sub-problems can include basic EC tasks such as logic cone comparison and/or state element mapping.