STACKABLE MULTI-CHIP PACKAGE SYSTEM

STACKABLE MULTI-CHIP PACKAGE SYSTEM

A stackable multi-chip package system is provided including forming an inter-chip structure adjacent to an external interconnect having both a base and a tip; connecting a first integrated circuit die and an outer portion of the base with the first integrated circuit die mounted over the inter-chip...

Ausführliche Beschreibung

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Bibliographische Detailangaben
1. Verfasser: YEE JAE HAK
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:A stackable multi-chip package system is provided including forming an inter-chip structure adjacent to an external interconnect having both a base and a tip; connecting a first integrated circuit die and an outer portion of the base with the first integrated circuit die mounted over the inter-chip structure, connecting a second integrated circuit die and an inner portion of the base with the second integrated circuit die mounted under the inter-chip structure, and molding the first integrated circuit die, the second integrated circuit die, and the external interconnect partially exposed.