Method of optimizing IC logic performance by static timing based parasitic budgeting

Increasing need to gain higher performance and lower power in semiconductor chips and field programable gate arrays requires that optimization be done in a constructive manner with respect to physical layout. Increasing perfomance by parasitic budgeting which dictates what parasitics are acceptable...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	CHEN CHAOIANG, JANAC J. G
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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