Method of optimizing IC logic performance by static timing based parasitic budgeting

Increasing need to gain higher performance and lower power in semiconductor chips and field programable gate arrays requires that optimization be done in a constructive manner with respect to physical layout. Increasing perfomance by parasitic budgeting which dictates what parasitics are acceptable to meet timing and power goals is presented. Providing these controls allows the physical implementation system to skew connection parasitics in a way that makes critical components and their connections significantly faster then those in the rest of the circuit. This represent a unique advantage of existing methods and provide a unique methods to reach higher levels of performance and lower power then existing approaches.