System and method for producing a semiconductor circuit arrangement

Method and systems for producing a semiconductor circuit arrangement are disclosed. In one implementation, after a formation of a first electrically conductive layer at the surface of a semiconductor substrate for the purpose of realizing a base connection layer and a first split gate layer, an implantation mask is formed for the purpose of carrying out a first collector implantation for the purpose of forming a collector connection zone. After the formation of a hard mask layer and a first etching mask, the hard mask layer is patterned and an emitter window is uncovered using the patterned hard mask layer. Using the patterned hard mask layer a second collector implantation is effected for the purpose of forming a collector zone, a base layer being formed in the region of the emitter window. Afterward, using a second etching mask, a field effect transistor region is uncovered and the patterned hard mask layer is removed in this region in order finally to form a second electrically conductive layer over the whole area for the purpose of realizing an emitter layer and a second split gate layer. Both the bipolar transistor and the field effect transistor are subsequently completed in a customary manner, in particular a source/drain implantation being used simultaneously for the doping of the emitter layer. Since the gate is deposited in two layers, the first layer simultaneously serving as base connection layer and the second layer simultaneously serving as emitter layer, up to two lithography planes can be obviated and costs can thereby be saved.