Fault tolerant computing system
A system for tolerating a single event fault in an electronic circuit is disclosed. The system includes a main processor that controls the operation of the system, a fault detection processor responsive to the main processor, and three or more programmable logic devices responsive to the fault detec...
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| Format: | Patent |
| Sprache: | eng |
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| Zusammenfassung: | A system for tolerating a single event fault in an electronic circuit is disclosed. The system includes a main processor that controls the operation of the system, a fault detection processor responsive to the main processor, and three or more programmable logic devices responsive to the fault detection processor. The three or more programmable logic devices periodically issue independent input signals to the fault detection processor for determination of one or more single event fault conditions. |
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