Edge pad architecture for semiconductor memory

A memory includes a wafer having at least a first and second edge, at least one memory bank array, a data path, and a plurality of data pads. The data path is coupled to the memory bank array. The plurality of data pads are coupled to the data path and configured with the data path to bus data to and from the memory bank array. The data pads are further configured such that each of the data pads are located adjacent the first and second edges of the wafer. The memory component is configurable for alternative applications such that in a first application all of the data pads used to bus data are located only on the first edge of the wafer and such that in a second application at least one of the data pads used to bus data is located on the first edge of the wafer and at least one of the data pads used to bus data is located on the second edge of the wafer.