Method for checking the pattern density of a semiconductor chip design with variable checking box size and variable stepping distance

A method for checking the pattern density of a chip layout is described. Initially, the design area is subdivided into a plurality of large checking boxes. Large portions of the chip are discarded from further checking if they are found to fall within acceptable limits at the more stringent and scal...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	SCHNABEL CHRISTOPHER M, SANDERSON DAVID I
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION ORPROCESSING OF GOODS COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS HANDLING RECORD CARRIERS PHYSICS PRESENTATION OF DATA RECOGNITION OF DATA RECORD CARRIERS TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINSTCLIMATE CHANGE
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