Method for checking the pattern density of a semiconductor chip design with variable checking box size and variable stepping distance

A method for checking the pattern density of a chip layout is described. Initially, the design area is subdivided into a plurality of large checking boxes. Large portions of the chip are discarded from further checking if they are found to fall within acceptable limits at the more stringent and scaled box size. The box size is successively reduced using an appropriate density for each box size until key problem areas are identified on the chip. After the check of a non-failing area, the reduction in checking box size is determined by the detected pattern density. Once the checking box size approximates that of the checking box size as dictated by the groundrule, the checking box size is fixed to that of the groundrule. Rather than using steps that are of the order of the width of the checking box, the box is stepped in an adaptive manner where the distance stepped is relative to the measured pattern density to guarantee that all the errors are captured and reported, regardless of their location from the origin.