Convolutional interleaving and de-interleaving circuit and method thereof

A convolutional interleaving and de-interleaving circuit and the method thereof are disclosed. The convolutional interleaving and de-interleaving circuit comprises an initial address generator, a first address generator, a second address generator, an address mixer, an adder, a controller and a memory. Wherein, the controller enables those address generators to provide or store corresponding channel addresses. Further, an adder is shared and memory addresses are appropriately arranged so as to reduce the requirement of registers. Accordingly, the required gate count and the chip layout area can be reduced.