Semiconductor wafer level chip package and method of manufacturing the same

Semiconductor wafer level chip package and method of manufacturing the same

A semiconductor chip package may include one or more conductive patterns provided on a front surface of a wafer. An encapsulation layer may cover at least the front surface of the wafer. Chip plugs may be electrically connected to the conductive patterns, and may be embedded in a rear surface of the...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: KIM HEUI-SEOG, KIM GOON-WOO, KIM JAE-HONG, KIM SANG-JUN, HAN MAN-HEE, SIN WHA-SU
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:A semiconductor chip package may include one or more conductive patterns provided on a front surface of a wafer. An encapsulation layer may cover at least the front surface of the wafer. Chip plugs may be electrically connected to the conductive patterns, and may be embedded in a rear surface of the wafer. External connection terminals may be electrically connected to the chip plugs, and may be provided on the rear surface of the wafer.