Memory control unit with configurable memory encryption

An electrical circuit includes a first interface for coupling to a data processor bus; a second interface for coupling to a memory; at least one data encryption engine and storage for storing a data structure specifying, for individual ones of a plurality of partitions of the memory, whether use of the at least one encryption engine for data read operations and data write operations is enabled for the associated partition and, if it is, information descriptive of at least one input to the encryption engine for that partition, comprising information related to a plurality of counters individual ones of which count write operations to an individual one of a plurality of data units storable in that partition.